The present invention relates to integrated circuits containing both N-channel and P-channel insulated gate field effect transistors (CMOS integrated circuits).
The merits of CMOS technology have been well established. It has also been shown that a vertical structure which stacks the P-channel transistor on top of the N-channel transistor is extremely area efficient and is attractive for high-density memory and logic circuits. However, the major disadvantage of all stacked CMOS structures which have been investigated so far is that the P-channel top device is not self aligned to the N-channel underlying device.
That is, a great advantage of conventional technology is that the source and drain implants are screened by the gate, so that, after the source/drain implants have been driven in, the gate is automatically self aligned to the lightly doped (p-type) space between the source and drain regions, which defines the channel regions of the device.
However, in a structure where a single gate electrode is used to address both an N-channel device in the silicon substrate and a polysilicon P-channel device, no such way to automatically align the location of the channel region of the P-type device to the common gate level has been found in the art. Misalignment can result in tremendously increased series resistance for the polysilicon device. This is particularly unfortunate since the series resistance of polysilicon devices in the prior art is already extremely high. Moreover, misalignment can also result in an excessively short effective channel region, so that the device exhibits poor subthreshold behaviour (soft turn off). Again, soft turn off is already a difficulty of the prior art polysilicon transistor, and it is very important not to exacerbate this inherent source of possible difficulties.
Thus, it is an object of the present invention to provide a stacked CMOS device structure, wherein a common gate level is self aligned both to MOS transistor having a channel region in a monocrystalline substrate and also to a separate transistor having a polycrystalline channel region.
It is a further object of the present invention to provide a device wherein a common gate electrode is self-aligned both to an N-channel transistor and also to at least one P-channel transistor.
It is the further object of the present invention to provide a stacked CMOS structure wherein good turn-off characteristics are exhibited by both N-channel and P-channel devices.
It is a further object of the present invention to provide a stacked CMOS structure wherein good turn-off characteristics are exhibited by the polysilicon transistor.
It is a further object of the present invention to provide a stacked CMOS device structure wherein acceptably low series resistance is provided in the polysilicon transistor.
To achieve these and other objects, the present invention provides a CMOS device configuration in which a complete CMOS inverter is contained in the space normally required for a single NMOS transistor of equivalent geometry. A first polysilicon layer of normal thickness and N+ doping is used for the N channel gate, and a second polysilicon layer is deposited conformally over the oxide which encapsulates the first polysilicon layer. The second polysilicon layer is thin and doped p-type. The second layer is only lightly doped initially, and is then doped more heavily by a shallow implantation. Portions of the second polylayer which are adjacent to the sidewalls of the gate electrode will be shielded from the implantation, and will therefore remain relatively lightly doped p-type channel regions, to form a pair of PMOS polysilicon transistors addressed by the N+ first poly gate electrode. Preferably the channel doping of these polysilicon transistors is at least 1017. Silicide strapping is optionally used on the remainder of the second polysilicon level to improve its conductivity.